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precision analog microcontroller, tunable optical control microcontroller data sheet ADUCM310 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 C 2017 analog devices, inc. all rights re served. technical support www.analog.com features analog input/output 22 -c hannel , 14 - bit, 800 k sps analog - to - digital converter ( adc ) 10 e xternal c hannels 1 o n- chip d ie t emperature m onitor 6 current output digital - to - analog converter ( idac ) m onitor c hannels 3 p ower m onitor c hann el s 2 b uffered re ference output channels fully differential and single - ended modes 0 v to 2.5 v analog input range 6 low n oise , 12 -/ 14 -b it idac outputs 1 250 ma, 1 200 ma, 2 10 0 ma, and 2 20 ma semiconductor optical amplifier (s oa ) idac pull - down to ? 3.0 v for fast current sink eight 12- bit voltage output dacs (vdac s) channel 0 and channel 1: 0 v to 3 v, 75 ? load channel 2 and channel 3: ?5 v to 0 v, 500 ? load channel 4 and channel 5: 0 v to 3 v, 300 ? load chann el 6: 0 v to 5 v, 500 ? load channel 7: 0 v to 5 v, 100 ? load 2.5 v, o n- chip voltage reference 2 b uffered 2.5 v output s microcontroller arm cortex - m3 processor , 32 - bit risc archi tecture s erial wire port s upports code download and debugging clocking options trimmed on - chip oscillator (3%) 80 mhz phase - locked loop ( pll ) external 16 mhz crystal option external clock source memory 2 12 8 kb f lash/ee memor ies , 32 kb sram in - ci rcuit download, sw - dp - based debug ging software triggered in - circuit reprogrammability on - chip peripherals uart, 2 i 2 c and 2 spi serial input/output 28- pi n general - purpose input/output ( gpio ) port 3 general - purpose timers wake - up (w/u) timer w atchdog timer (wdt) 32- element p rogrammable l ogic a rray (pla) vectored interrupt controller interrupt on edge or level external p in inputs 9 e xternal i nterrupts power multiple s upplies 5 v for vdac6 and vdac7 3 .3 v for digital and analog input s /output s 1. 8 v to 2. 7 v for idacs ?5 v supply for i dac 3 and vdac 2 /vdac 3 package and temperature range 6 mm 6 mm , 112 -b all csp_ bga package fully specified for ? 40 c to + 8 5c ambient operation tools quickstart? development system full third p arty support applications optical m odules t unable l aser modules functional block dia gram reset iovddx pvdd_idacx avddx dgndx swdio swclk pgnd ADUCM310 por on-chip 1.8v ldo 32.786khz 16mhz osc 80mhz pll arm cortex-m3 processor 2.5v band gap v ref memory 256k flash 32k sram dma nvic pla 32 elements gpio ports uart port 2 spi port 2 i 2 c port ext irqs 3 gp timer wd timer w/u timer pwm serial wire general- purpose i/o ports idac idac buf ain0 ain9 vdac vdac0 idac0 idac5 vdac vdac7 14-bit sar adc internal channels, idacs, temperature, supplies mux vref_1.2 buf_vref2.5a buf_vref2.5b 13040-001 f igure 1.
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ADUCM310 data sheet rev. b page 2 of 27 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 timing specifications ................................................................ 12 absolute maximum ratings .......................................................... 17 thermal resistance .................................................................... 17 esd caution ................................................................................ 17 pin configuration and function descriptions ........................... 18 typical performanc e characteristics ........................................... 22 recommended circuit and component values ........................ 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 7/20 1 7re v. a to rev. b ch ange to features ........................................................................... 1 change to general description ...................................................... 3 changes to specifications section and table 1 ............................. 4 added endnote 1, table 1; renumbered s equentially .............. 12 11/ 2015 re v. 0 to rev . a change to features section ............................................................. 1 change s to specifications section and table 1 ............................. 4 changes to table 6 and figure 5 ................................................... 15 changes to table 7 and figure 6 ................................................... 16 changes to figure 7 ........................................................................ 18 5/ 2015 re vision 0: initial version
data sheet ADUCM310 rev. b page 3 of 27 general description the ADUCM310 is a multi die stack , on - chip s ystem designed for diagnostic cont rol of tunable laser op tical module applications . the ADUCM310 features a 16 - bit (14 - bit accurate) multichannel successive approximation register ( sar ) adc, an arm cortex ?- m3 processor, eight voltage dacs (vdacs) , six current output dacs, and flash/ee memory packaged in a 6 mm 6 mm , 112 -ball csp_ bga package. the bottom die in the stack supports the bulk of the low voltage analog circuitry and is the largest of the three die. it contains the adc, vdac s , main idac circuits , as well as other analog support circuits , such as the l ow drift precision 2.5 v voltage reference source. the middle die in the stack supports the bulk of the digital circuitry , including the arm cortex - m3 processor, the flash and sram blocks , and all of the digital communication peripherals. in addition, thi s die provide s the clock sources for the whole chip. a 16 mhz internal oscillator is the source of the internal pll that outputs an 80 mhz system clock. the top die, which is the smallest die, was developed on a high voltage process , and this die su pport s the ? 5 v and +5 v vdac outputs. it also implements the soa idac current sink circuit that allows the external soa diode to pull to a ?3.0 v level to implement the fast shutdown of the laser output . regarding the individual blocks, the adc is capable of ope rating at conversion rates up to 800 k sps. there are 10 external inputs to the adc , which can be single ended or differential. several internal channels are included , such as the supply monitor channels, an on - chip temperature sensor , and internal voltage reference monitor s. the v dacs are 12 - bit string dacs with output buffers capable of sourcing between 10 ma and 50 ma , and these dacs are all capable of driving 10 nf capacitive loads. the low drift c urrent dacs have 14 - bit resolution and varied full -scale output ranges from 0 ma to 20 ma to 0 ma to 250 ma on the soa idac (idac3) . t he soa idac also comes with a 0 ma to ?8 0 ma current sink capability. a precision 2.5 v on - chip reference source is available. the internal adc, idacs, and vdac circuits use this on - chip reference source to ensure low drift performance for all of these peripherals the ADUCM310 a lso provide s 2 buffered reference outputs capable of sourcing up to 1.2 ma. these outputs can be used externally to the chip. the ADUCM310 integrates an 80 mhz arm cortex - m3 processor. it is a 32 - bit reduced instruction set computer ( ri sc ) machine, offering up to 100 dmips peak pe rformance. the arm cortex - m3 processor also has a flexible 14 - channel direct memory access ( dma ) controller supporting serial peripheral interface (spi), uart, and i 2 c communication peripherals . the ADUCM310 has 256 kb of nonvolatile flash/ee memory and 32 kb of sram integrated on - chip. a 16 mhz on - chip oscillator generates the 80 mhz system clock. this clock internally divide s to allow the processor to operate at lower frequency , thus saving power. a low power internal 32 khz oscillator is available and can clock the timers. the ADUCM310 includes t hree general - purpose timers, a wake - up timer (which can be used as a general - purpos e timer) , and a system watchdog timer . a range of communication peripherals can be configured as required in a specific application. these peripherals include ua rt, 2 i 2 c, 2 spi, gpio ports , and pulse - width modulation ( pwm ). on - c hip factory firmware supports in - circuit serial download via the uart , while nonintrusive emulation and program download are supported via the serial wire debug port (sw - dp) interface. these features are supported on the e va l - ADUCM310qspz development system. the ADUCM310 o perates f rom 2.9 v to 3.6 v and is s pecified over a t emperature range of ?4 0c to + 85c. n ote that, throughout this data sheet, multifunction pins, such as p1.0/sin/eclkin/plai[4] , are referred to either by the entire pin name or by a single function of the pin, for example, p1.0 , when only that f unction is relevant. for additi onal information on the ADUCM310 , see the ADUCM310 reference manual, how to set up and use the ADUCM310 .
ADUCM310 data sheet rev. b page 4 of 27 specifications av dd = iov dd = dv dd = 2.9 v to 3.6 v (the input supply voltages) . the d ifference between av dd , iov dd , and dv dd must be 0.3 v. av neg (the supply voltage) = ?5.5 v to ? 4.65 v. vdacv dd (the vdac supply voltage) = 3.07 v to 5.35 v (for vdac6 and vdac7) , and vdacv dd must be av dd . pv dd (the idac supply voltage) for the idacs = 1.8 v to 2.7 v. av dd pv dd + 0.4v. v ref = 2.5 v internal reference, f core = 80 mhz, t a = ?40 c to +85 c, unless otherwise noted. for power sequencing, connect the agnd, dgnd, pgnd, and iognd pins to ground before applying power to the av neg or vdacv dd pins . for register and bit information, see the ADUCM310 reference manual, how to set up and use the ADUCM310 . table 1. parameter min tp ma nit test condi tions/comments adc channel specifications all m easurements in single - ended mode , unless otherwise stated adc power - up time 5 s f sample 500 ksps dc accuracy resolution 14 bi ts integral nonlinearity input buffer disabled 2 lsb 2.5 v internal reference 1.5 1 lsb 2 .5 v internal reference enabled 2.5 lsb disabled 2 lsb e xternal reference 1.5 1 lsb e xternal reference differential nonlinearity ? 0.99 0. 7 +1 .5 1 lsb 2.5 v ex ternal reference ; n o missing codes ?0. 99 0.7 +2.0 lsb 2.5 v ex ternal reference; no missi ng codes dc code distribution 3 lsb adc input voltage = 1.25 v dc 5 endpoint errors offset error ( all channels e xcept the internal c hannels ) ad c update rate up to 8 00 ksps buffer o n or buffer o ff ? 0. 8 0.2 + 0. 8 mv buffer on, chop mod e on and automatic zero or buffer off ?0. 6 1 0.2 +0. 6 1 mv buffer on, chop mode on and automatic zero or buffer off offset error drift 2 buffer on or buffer o ff 3.2 v/ c buffer on, c hop mode on and a utomatic zero or b uffer off 2.5 1 v/ c buffer on, chop mode on and automatic zero or buffer off full - scale error ad c upate rate up to 00 sps buer o n or buer o 0 0 0 v e cluing internal channels 0 1 0 0 1 v ecluing internal channels internal c hannels 0 1 o ull scale input buer on av dd , iov dd , pv dd oltage on pvddidac pin 0 0 1 o ull scale input buer on av dd , iov dd , pv dd oltage on pvddidac pin 0 o ull scale input buer on idac0 to idac easure ith 1 v on the idac0 to idac pin s 0 1 1 o ull scale input buer on idac0 to idac easure ith 1 v on the idac0 to idac pins gain error drit v c full scale error rit inus oset error rit a ll oes i nternal reerence
data sheet ADUCM310 rev. b page 5 of 27 parameter min typ max unit test condi tions/comments dynamic performance 2 f in = 665.283 hz sine wave ; f sample = 100 k sps; i nternally unbuffered channels ; the f ilter on the analog inputs is a 15 ? resistor and a 2 nf capacitor signal -to - noise ratio (snr) input buffer disabled 80 db incl udes distortion and noise components enabled 78 db ch op mode on 74 db aut o matic z ero total harmonic distortion (thd) input buffer disabled ? 86 db enabled ? 86 db ch op mode on and automatic zero peak harmonic or spurious noise ? 88 db buf fer on and off channel - to - channel crosstalk ? 95 db me asured on adjacent channels ; f in = 25 k hz sine wave; b uffer on and off analog input absolute input voltage range unbuffered mode agnd av dd v voltage level on ainx pin buffered mode agnd + 0.15 2.5 v voltage level on ainx pin input voltage ranges differential mode ?v ref +v ref v voltage difference between ain+ (posit ive input) and ain ? ( negative input ) common - mode voltage range 0.9 1.6 v single - ended mode agnd v ref v voltage difference between ain+ and ain ? input current 3 buffered mode v in = 0.15 v to 2.5 v ain0, ain1, ain2 , and ain3 ? 10 2 5 + 13 2 na adc sampling rate 100 ksps ? 40 15 + 60 na adc sampling rate 500 ksps ? 60 2 25 + 90 2 na adc sampling rate 800 ksps input current d rift 20 pa/ c input buffer on, adc sampling rate 500 ksps 1 0 1 pa/ c input buffer on, adc sampling rate 500 ksps 34 pa/ c inp ut buffer on, adc sampling rate 800 ksps 20 1 pa/ c input buffer on, adc sampling rate 800 ksps ain4 to ain9 ? 50 2 20 + 50 2 na ain4 to ain9 100 ksps ? 215 2 50 +110 2 na adc sampling rate 500 ksps ? 350 2 ? 90 +90 2 na adc sampling rate 800 ksps unbuffered mode ? 1100 2 + 750 + 1700 2 na v in = 0 v to 2.5 v, a ll channels, all sampling rates in put current d rift 1 40 1 pa/ c v in = 1 v 5 30 pa/ c v in = 1 v input capacitance 20 pf du ring adc acquisition , buffer on input leakage current ? 1.6 2 +1 + 3.5 2 na adc off, buffer off or buffer on, ainx connected 2.5 v
ADUCM310 data sheet rev. b page 6 of 27 parameter min typ max unit test condi tions/comments on - chip voltage reference 0.47 f from vref_1.2 to agnd output voltage 2.505 v accuracy 4 5 mv t a = 25c reference temperature coefficie nt 2 , 5 15 30 1 ppm/c 15 44 ppm/c power supply rejection ratio 70 db output impedance 3 ? fo r adc_capp, t a = 25c internal v ref power - on time 2 38 50 ms tur ned on by default external reference input 2 input voltage range 2 1.8 2.5 v adc maximum reference voltage = 2.5 v switching time external to internal reference 2.5 ms internal to external reference 1 ms buffered vref outputs (buf_vref2.5x pins) output voltage 2.5 v accurac y 5 mv t a = 25c, load = 0.4 ma reference temperature coefficient 2 15 30 1 ppm /c 100 nf capacitor required on both outputs 15 50 ppm/ c load regulation 2.5 mv/ ma output impedance 3 ? t a = 25c load current 1.2 ma power supply rejection ratio 70 db idac channel specifications 6 , 7 voltage compliance range 2 ou tput voltage compliance ; m inim um compliance if idac x set to full scale, see figure 15 to figure 20 idac0, idac1, and idac2 0.4 pv dd ? 200 mv pv dd C 275 mv v idac4 and idac5 0.4 pv dd C 200 mv v ida c3 0.5 pv dd ? 450 mv v ?3.7 ?3.0 v at ?3.5 v, maximum sink current is 80 ma; pin voltage clamped to ?3.5 v, tolerance of clamping voltage is 200 mv reference current generator reference current 0.38 ma usin g internal reference, 0.1%, 5 ppm , 3.16 k? external resistor idac reference current shutdown threshold 0.76 ma i f t he external resistor (r ext ) value drops below 1.580 k?, idac output currents disable temperature coefficient 2 , 5 7 25 ppm/ c using internal reference ; over heat shutdown 135 c junction temperature resolution idac0, idac1, idac4,and idac5 14 bi ts 11- bit msbs and 5 - bit lsbs are guaranteed monotonic idac2 14 bi ts 11- bit msbs and 5 - bit lsbs are guaranteed monotonic idac3 14 bits 0 v to 2 v compliant range, 11 - bit msbs and 5 - bit lsbs are guaranteed monotonic idac3 8 bi ts ?4.5 v to 0 v compliant range
data sheet ADUCM310 rev. b page 7 of 27 parameter min typ max unit test condi tions/comments full - scale output idac0 and idac1 100 ma idac4 and idac5 20 ma idac2 200 ma idac3 250 ma current source ?90 cur rent sink ?80 1 cur rent sink integral nonlinearity ?3 1.5 +4 lsb 11- bit ? 2.5 1 1.5 +4 lsb 11- bit noise current rm s noise; maximum bandwidth setting, idacxcon[5:2] = 0000b idac0 and idac1 1.5 a mea sured driving 10 ? idac4 and idac5 0.3 a mea sured driving 100 ? idac2 4 a mea sured driving 5 ? idac3 5 a mea sured driving 5 ? full - scale error idac 0 and idac1 ? 2.3 1 0.25 +1 1 % ?3. 0 0.25 +1.3 % idac 4 and idac 5 ? 0.7 1 0.25 0.7 % ?1 0.25 + 0.7 % idac2 ? 1.75 1 0.25 0.65 % ?1. 77 0.25 % idac3 ?2 1 0.25 1.4 1 % ?2. 4 0.25 + 1.6 % full - scale error drift vs. temperature including internal reference drift and 5 ppm external resistor idac4 and idac5 ?40 1 ?12 + 30 1 ppm/c ?58 ? 12 +58 ppm/c idac2 and idac3 +55 ppm/ c full temperature range idac2 and idac3 +40 ppm/ c reduced 25c to 85c range idac0 and idac1 ?145 1 +55 1 +145 1 ppm/c ?205 + 90 +205 ppm/c full temperature range idac0 and idac1 ?100 +40 +100 ppm/c reduced 25c to 85c range full - scale error drift vs. time 8 lon g - term stability idac0 200 a/ 100 0 hours idac1 450 a/ 100 0 hours idac2 500 a/ 100 0 hours idac3 2250 a/ 100 0 hours idac4 and idac5 40 a/ 100 0 hours zero - scale error pul l - down current off idac0 an d idac1 ? 120 1 +75 1 a ?180 +115 a pull - down current ? 135 ?115 ?100 a increased ?45c to +85c range idac4 and idac5 ? 25 1 +15 a ?31 +15 a pull - down current ? 30 ?24 ? 22 a
ADUCM310 data sheet rev. b page 8 of 27 parameter min typ max unit test condi tions/comments idac2 and idac3 ?350 1 + 280 1 a ?460 +300 a pull - down current for idac2 ? 300 ?288 ? 160 a zero - scale error drift 2 idac0 and idac1 ? 850 1 300 + 1200 1 na/c ?140 0 300 +1400 na/c idac4 and idac5 ?120 50 +205 1 na/c ?120 50 +230 na/c idac2 and idac3 1 a/ c settling time idac0, idac1, idac2, and idac3 1 ms t o 0.1%, idacxcon[5:2] = 0101b, 1 ma change in output cur rent idac4 and idac5 2 ms idac0, idac1, idac2, and idac3 250 s to 1%, idacxcon[5:2] = 0101b, 1 ma change in output current idac4 and idac5 1.2 ms idac0, idac1, idac2, and idac3 50 s to 1%, idacxcon[5:2] = 0000b, 1 ma change in output curr ent idac4 and idac5 1.1 ms idac3 switching time 2 1 s time to switch from current source to current sink transconductance an alog input signal coupled on to cdamp_idacx pin via 1 nf capacitor; freque ncy range = 100 khz to 1000 khz; voltage is the peak to peak voltage on the cdamp_idacx pin of the associated idac; current is peak -to - peak current change idac0 and idac1 7.99/ 100 ma/ mv idac2 12.6/100 ma/mv idac3 18.6/ 100 ma/ mv idac4 and idac5 1.16/ 100 ma/ mv idac shutdown temperature 125 c die t emperature; enabled via idacxcon[6] vdac channel specifications 6 , 9 , 10 dc accuracy resolution 12 bi ts relative accuracy vd ac0, vdac1, and vdac2 ?6 .3 1 +10 lsb vdac4 and vdac5 ?7 .3 2 +11 lsb vdac3, vdac6, and vdac7 ?7 2 +8 .5 lsb differential nonlinearity ?0.99 0.6 +1 lsb guaranteed monotonic offset error calculated 5 mv 2.5 v internal reference actual mea sured at code 0 vdac0, vdac1, vdac4, and vdac5 4 7 mv vdac6 and vdac7 15 22 mv vdac2 and vdac3 ?30 ?20 mv full - scale error 0. 7 1 % of full scale for vdac2, vdac3, vdac4, vdac5, and vdac6 0. 9 % of full scale for vdac2, vdac3, vdac4, vdac5, and vdac6 vdac0, vdac1, and vdac7 2 0. 7 1 % with 500 ? load 0. 9 % with 500 ? load
data sheet ADUCM310 rev. b page 9 of 27 parameter min typ max unit test condi tions/comments vdac0 and vdac1 0.5 % wit h 75 ? load, over full temperature range vdac7 0. 5 % wit h 100 ? load, over full temperature range gain mismatch error 0.1 % vdac0 relative to vdac1 0.2 % vda c2 relative to vdac3 0.1 % vda c4 relative to vdac5 0.35 % vda c6 relat ive to vdac7; both driving a 500 ? load offset error drift calculated vdac0, vdac1, vdac4, and vdac5 5 v/ c vdac2, vdac3, vdac6, and vdac7 25 v/ c actual mea sured at code 0 vdac0, vdac1, vdac4, and vdac5 13 v/ c vdac2, vdac3, vdac6, and vdac7 75 v/ c gain error drift ex cluding internal reference drift vdac0, vdac1, vdac4, and vdac5 5 ppm/ c vdac2, vdac3, vdac6, and vdac7 10 ppm/ c output impedance vdac0, vdac1, vdac4, vdac5, vdac6, and vdac7 1 ? vdac2 and vdac3 1.5 ? short - circuit current mea sured with vdac shorted to ground and to associated power supply vdac0 and vdac1 200 ma vdac2 and vdac3 170 ma vdac4 and vdac5 200 ma vdac6 and vdac7 200 ma vdac outputs ca pa citive load up to 0.01 f output impedance vdac0, vdac1, and vdac4 to vdac7 1.8 ? vdac2 and vdac3 1.2 ? output range bu ffer on vdac0 and vdac1 0 + actual offset 1 av dd C 600 mv v r l = 75 ? , 40 ma maximum, v out maximum = 3 v vdac2 and vdac3 av neg + 250 mv ?0. 15 v r l = 500 ?, 10 ma maximum, v out maximum = ?5 v, g ain = ?2.25 v vdac4 and vdac5 0 + actual offset 1 av dd C 300 mv v r l = 300 ?, 10 m a maximum, v out maximum = 3 v vdac6 0 + actual offset 1 vda cv dd ? 250 mv v r l = 500 ?, 10 ma maximum, v out maximum = 5 v vdac7 0 + actual offset 1 vda cv dd ? 700 m v v r l = 100 ?, 50 ma maximum, v out maximum = 5 v
ADUCM310 data sheet rev. b page 10 of 27 parameter min typ max unit test condi tions/comments dac ac characteristics slew rate vdac0, vdac1, vdac4, and vdac5 3 v/s vdac2, vdac3, and vdac6 1.1 v/s voltage output settling time 10 s loa d =100 pf 0.05 ms loa d = 0.01 f di gital -to - analog glitch energy 20 nv/ sec 1 lsb change at major carry (dacxdat register change from 0x07ff0000 to 0x08000000) ac psrr 100 hz vdac0, vdac1, vdac4, and vdac5 72 db vdac2 and vdac3 67 db vdac6 and vdac7 64 db ac psrr 1 khz vdac0, vdac1, vdac4, and vdac5 56 db vdac2 and vdac3 53 db vdac6 and vdac7 50 db power - on reset (por) refers to voltage at dvdd pin por trip level 2.80 2.85 2.9 v power - on level 2.74 2.79 2. 83 v power - down level por hysteresis 65 mv external reset external reset minimum pulse width 2 1.5 s mini mum pulse width required on external reset pin to trigger a reset sequence reset pin glitch immunity 2 50 ns maxi mum low pulse width on reset pin that does not generate a reset temperature sensor accuracy 2 1.25 1.37 1.494 v indicates die temperature; adc measured voltage for temperature sensor channel without calibration, t a = 25c flash/ee memory endurance 10,000 cycl es data retention 20 years t j = 85c internal high power oscillator 16 mhz accuracy ? 2 .2 5 1 +2 .2 5 1 % used as input to pll to generate 80 mhz clock ?3.0 +3 % internal low power oscillator 32.768 khz accuracy ?12 1 8 +12 % ?22 8 +12 logic inputs input low voltage (v inl ) 0.2 i ov dd v in put high voltage (v inh ) 0.7 iov dd v short - circuit current 2 12 ma logic outputs output high voltage (v oh ) 11 iov dd ? 0.4 v i source = 2 ma output low voltage (v ol ) 11 0.4 v i sink = 2 ma short - circuit current 2 12 ma
data sheet ADUCM310 rev. b page 11 of 27 parameter min typ max unit test condi tions/comments input leakage current logic 1 80 a v inh = 3.6 v internal pull - up disabled ?22 +6 +2 2 na logic 0 80 a v inh = 0 v interna l pull - up disabled ?22 +6 +22 na pull -up 30 40 72 k? if not disabled, disabled at reset; pull - up can be described as an 80 a (typical) current source crystal inputs xclki and xclko (16 mhz) logic inputs, xclki only input low voltage (v inl ) 1.1 v input high voltage (v inh ) 1.7 v xclki input capacitance 8 pf xclko output capacitance 8 pf microcontroller unit clock rate using pll output 2 0.05 80 mhz processor start - up time at power - on 2 38 50 ms in cludes kernel power - on execution time after reset event 1.44 ms in cludes kernel power - on execution time after processor power down mode 1, mode 2, or mode 3 3 to 5 f clk power requirements power supply voltage range av dd 2.9 3.3 3.6 v measured between avdd x and agnd iov dd 2.9 3.3 3.6 v measured between iovddx and agnd analog power supply currents av dd current 6.5 7.2 ma adc, vdacs, idacs off dig ital power supply current current in normal mode dv dd 29 32 ma cl kcon1[2:0] = [000b] iov dd 2.7 5.1 ma all gpio pull - ups enabled additional power supply currents adc 2 3.1 3.6 ma adc con tinuously converting at 100 ksps adc input buffer 2 4.1 4.8 ma both buffers enabled idac 2 26.5 30 ma dac 2 2.7 3. 1 ma total for all vdacs driving maximum allowed load with dacxdat = 0 vdac2 and vdac3 2 ?1. 7 ma i dd when vdac2 and vdac3 are driving maximum allowed load with dacxdat set to 0 vdac6 and vdac7 2 1 ma i dd sourced from the vdacv dd supply when vdac6 and vdac7 are driving the maximum allowed load wi th dacxdat set to 0 1 reduced temperature range of ? 10c to + 8 5 c. 2 these numbers are not production tested but are guaranteed by design or characterization data at production release. 3 the i nput current is the total input current including the input pad and mux leakage plus the charge current for the full input circuit. the i nput current r elate s to the adc sampling frequency.
ADUCM310 data sheet rev. b page 12 of 27 4 the internal reference calibration and trimming are performed when t he processor operat es in normal mode with cd = 0, when adc is enabled and converting, when idacs are all on , and when vdacs are on. v ref accuracy can vary under other operating conditions. 5 measured using the following box method : ( ) ( ) ( ) 6 1 2.5 ? ? minimume temperatur maximum e temperatur e temperatur any at minimum ve temperatur any at maximum v ref ref vdac inearity speiiations are auated with oowin ranes vdac0 and vdac 1 10 mv to v vdac and vdac 3 10 mv to v vdac and vdac 10 mv to v vdac 10 mv to v vdac 10 mv to v anao deies n prodution dac u sae trimmin onditions inude vdddacx pin otae 0 v a dacs on the on term staiity speiiations is nonumuatie the drit in suseuent 1000 hour periods is siniianty ower than in the irst 1000 hour period for a vdac speiiations or vdac0 vdac1 vdac and vdac dacxc10 11 10 vdacx mi nimum and maximum imits appy to the interna reerene ony dacxc10 00 avddx suppy aid ony with typia speiiations 11 the aerae urrent rom the pins must not exeed 3 ma per pin see fi ure timing specification s i 2 c timing t 2 i 2 c timing in sn s lave parameter description min typ max unit t l sclx low pulse width 4.7 s t h sclx high pulse width 4.0 ns t shd star t condition hold time 4.0 s t dsu data setup time 250 ns t dhd data hold time (sda x held internally for 300 ns after falling edge of scl x) 0 3. 45 s t rsu setup time for repeated start 4.7 s t psu stop condition setup time 4.0 s t buf bus free time between a stop condition and a start condition 4.7 s t r rise time for both scl x and sda x 1 s t f fall time for both scl x and sda x 15 300 ns t vd;dat data valid time 3. 45 s t vd;ack data valid acknowledge time 3.45 s t able 3 . i 2 c timing in fast mode (400 khz) s lave parameter description min typ max unit t l sclx low pulse width 1.3 s t h sclx high pulse width 0.6 ns t shd start condition hold time 0.3 s t dsu data setup time 100 ns t dhd data hold time (sda x held internally for 300 ns after falling edge of scl x) 0 s t rsu setup time for repeated start 0.6 s t psu stop condition setup time 0. 3 s t buf bus free time between a stop condition and a start condition 1.3 s t r rise time for bo th scl x and sda x 20 300 ns t f fall time for both scl x and sda x 15 300 ns t vd;dat data valid time 0. 9 s t vd;ack data valid acknowledge time 0. 9 s
data sheet ADUCM310 rev. b page 13 of 27 sdax (i/o) t buf msb lsb ack msb 1 9 8 2 to 7 1 sclx (i) p s s(r) repeated start start condition stop condition t r t f t f t r t h t vd;dat t l t dsu t dhd t rsu t dhd t dsu t shd t psu t vd;ack 13040-002 fig ure 2. i 2 c compatible interface timing spi timing table 4 . spi master mode timing (phase mode = 1) parameter description min typ max unit t sl sclk x low pulse width (sp i x div 1 + 1) t hclk 2 /2 ns t sh sclk x high pulse width (sp i x div 1 + 1) t hclk 2 /2 ns t dav data output valid after sclk x edge 0 3 ns t dsu data input setup time before sclk x edge ? s clk x ns t dhd data input hold time after sclk x edge sc lk x ns t df data output fall time sc lk x ns t dr data output rise time 25 ns t sr sclk x rise time 25 ns t sf sclk x fall time 20 ns 1 for spi0, x is 0 , and for spi1 , x is 1 . 2 t hclk is the divided syst em clock, uclk/clkcon1[2:0]. sclkx (polarity = 0) sclkx (polarity = 1) mosix msb bit 6 to bit 1 lsb misox msb in bit 6 to bit 1 lsb in t sh t sl t sr t sf t dr t df t dav t dsu t dhd 13040-003 fig ure 3 . spi master mode timing (phase mode = 1)
ADUCM310 data sheet rev. b page 14 of 27 table 5 . spi master mode timing (phase mode = 0) p arameter description min typ max unit t sl sclk x low pulse width (sp i x div 1 + 1) t hclk 2 /2 ns t sh sclk x high pulse width (sp i x div 1 + 1) t hclk 2 /2 ns t d av data output valid after sclk x edge 0 3 ns t dosu data output setup before sclk x edge ? s clk x ns t dsu data input setup time before sclk x edge sc lk x ns t dhd data input hold time after sclk x edge sc lk x ns t df data output fall time 25 ns t dr da ta output rise time 25 ns t sr sclk x rise time 20 ns t sf sclk x fall time 20 ns 1 for spi0, x is 0 , and for spi1 , x is 1. 2 t hclk is the divided system clock, uclk/clkcon1[2:0]. sclkx (polarity = 0) sclkx (polarity = 1) t sh t sl t sr t sf mosix msb bit 6 to bit 1 lsb misox msb in bit 6 to bit 1 lsb in t dr t df t dav t dosu t dsu t dhd 13040-004 fig ure 4 . spi master mode timing (phase mode = 0)
data sheet ADUCM310 rev. b page 15 of 27 table 6 . spi slave mode timing (phase mode = 1) parameter description min typ max unit t cs0 /t cs1 cs0 / cs1 to sclk x edge 10 ns t cs m cs0 / cs1 high time between active periods sc lkx ns t sl sclk x low pulse width (sp i x div 1 + 1) t hclk 2 ns t sh sclk x high pulse width (spi x div 1 + 1) t hclk 2 ns t dav data output valid after sclk x edge 20 ns t dsu data input setup time before sclk x edge 10 ns t dhd data input hold time after sclk x edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk x rise time 1 ns t sf sclk x fall time 1 ns t sfs cs0 / cs1 high after sclk x edge 20 ns 1 for spi0, x is 0 , and for spi1 , x is 1. 2 t hc lk is the divided system clock, uclk/clkcon1[2:0]. sclkx (polarity = 0) cs0/cs1 sclkx (polarity = 1) t sh t sl t sr t sf t sfs misox msb bit 6 to bit 1 lsb mosix msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t cs0 / t cs1 t csm 13040-005 fig ure 5 . spi slave mode timing (phase mode = 1)
ADUCM310 data sheet rev. b page 16 of 27 table 7 . spi slave mode timing (phase mode = 0) parameter descriptio n min typ max unit t cs0 /t cs1 cs0 / cs1 to sclkx edge 10 ns t cs m cs0 / cs1 high time between active periods sclkx ns t sl sclkx l ow pulse width (s pixdiv 1 + 1) t hclk 2 ns t sh sclkx high pulse width (spixdiv 1 + 1) t hclk 2 ns t dav data output valid after sclkx edge 20 ns t dsu da ta input setup time before sclkx edge 10 ns t dhd data input hold time after sclkx edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclkx rise time 1 ns t sf sclkx fall time 1 ns t docs data output valid after cs0 / cs1 edge 20 ns t sfs cs0 / cs1 high after sclkx edge 10 ns 1 for spi0, x is 0 , and for spi1 , x is 1 2 t hclk is the divided syst em clock, uclk/clkcon1[2:0]. sclkx (polarity = 0) sclkx (polarity = 1) t sh t sl t sr t sf t sfs misox mosix msb in bit 6 to bit 1 lsb in t dhd t dsu msb bit 6 to bit 1 lsb t docs t dav t dr t df t cs0 / t cs1 13040-006 cs0/cs1 t csm fig ure 6 . spi slave mode timing (phase mode = 0)
data sheet ADUCM310 rev. b page 17 of 27 absolute maximum rat ings t a = 25c , unless otherwise noted. table 8. parameter rating av dd to agnd x av neg to agndx vdacv dd to agndx iovdd x to dgnd x digital input voltage to dgndx digital output voltage to dgndx analog inputs to agndx total p ositive gpio p in s current total n egative gpio p in s current idac3 pull - down voltage i dac3 pull - down current operating temperature range storage temperature range junction temperature ? 0.3 v to + 3. 9 6 v ? 5.5 v to + 0.3 v ? 0.3 v to + 5.5 v ? 0 .3 v to + 3.96 v ? 0.3 v t o iov ddx + 0.3 v ? 0 .3 v to iovddx + 0.3 v ? 0.3 v to av dd + 0.3 v 0 ma t o 3 0 m a ? 30 ma t o 0 ma av neg ? 0.3 v ? 1 0 0 ma ?4 0c to +85c ? 65c t o + 150c 15 0 c esd rating, all pins human body model (hbm) 1 kv field - induced charged device model (ficdm) 1.25 kv stres ses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of th is specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 9 . thermal resistance package type ja jc unit 112- ball csp_ bga 44.5 11 c/w esd caution
ADUCM310 data sheet rev. b page 18 of 27 pi n configuration and function description s reserved idac0 pvdd_ idac0 idac2 pvdd_ idac2 idac3 pgnd pvdd_ idac3 pvdd_ idac1 idac1 reserved 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 idac4 cdamp_ idac0 cdamp_ idac2 idac2 pvdd_ idac2 idac3 pgnd pvdd_ idac3 cdamp_ idac3 cdamp_ idac1 idac5 pvdd_ idac4 cdamp_ idac4 p2.3/bm p1.0/ sin/ eclkin/ plai[4] p1.2/ pwm0/ plai[6] p1.3/ pwm1/ plai[7] p1.4/ pwm2/ sclk1/ plao[10] p1.5/ pwm3/ miso1/ plao[11] p1.6/ pwm4/ mosi1/ plao[12] cdamp_ idac5 pvdd_ idac5 reserved reset p3.2/ plai[14] p2.0/irq2/ pwmtrip/ placlk2/ plai[8] p1.1/sout/ placlk1/ plai[5] reserved p2.4/irq5/ adcconv/ pwm6/ plao[18] p2.5/irq6/ pwm7/ plao[19] p1.7/irq1/ pwm5/cs1/ plao[13] dgnd2 iref iovdd1 p0.1/ miso0/ plai[1] p0.0/ sclk0/ plai[0] p2.2/irq4/ mrst/ clkout/ plai[10] p2.1/irq3/ pwmsync/ plai[9] swdio swclk iovdd2 iognd1 p0.3/ irq0/cs0/ plai[3] p0.2/ mosi0/ plai[2] reserved ADUCM310 top view (not to scale) reserved vdacv dd avdd_reg1 iognd2 p0.7/ sda1/ plao[5] p0.6/ scl1/ plao[4] p0.5/ sda0/ plao[3] p.04/ scl0/ plao[2] ain4 agnd2 avdd_reg2 vref_1.2 p2.6/ irq7/ plao[20] p2.7/ irq8/ plao[21] p3.0/ plai[12] agnd5 vdac5 reserved ain1 ain5 vdac6 vdac7 avdd4 p3.4/ plao[26] xtalo p3.1/ plai[13] vdac4 dvdd ain0 ain2 ain6 vdac2 buf_ vref2.5a agnd4 iovdd3 xtali dvdd_reg1 vdac1 agnd1 av neg ain3 ain7 vdac3 adc_capn buf_ vref2.5b iognd3 a b c d e f g h j k l idac related digital pins analog pins reserved a b c d e f g h j k l dgnd1 dvdd_reg2 vdac0 avdd3 agnd3 agnd6 ain8 ain9 adc_capn adc_capp 13040-007 figure 7 . pin configuration table 10 . pin function descriptions pin no. mnemonic type 1 description d2 reset i reset input (active low). an int ernal pull - up is included on this pin . e3 p0.0/sclk0/plai[0] i/o general - purpose input and output port 0.0/spi0 clock /input to pla e lement 0. this pin d efaults as an input with the internal pull - up resistor disabled. e2 p0.1/miso0/plai[1] i/o general - pur pose input and output port 0.1/spi0 d ata master in put - slave output/input to pla e lement 1. this pin defaults as an input with the internal pull - up disabled. f3 p0.2/mosi0/plai[2] i/o general - purpose input and output port 0.2/spi0 data ma ster o utput - slave input/input of pla e lement 2. this pin defaults as an input with the internal pull - up disabled. f2 p0.3/irq0/ cs0 /plai[3] i/o general - purpose input and output port 0.3/external interrupt reque st 0/ spi0 chip select inp ut/input of pla e lem ent 3. this pin defaults as an input with the internal pull - up disabled. if spi0 is used, configure this pin as cs0 . g4 p0.4/scl0/plao[2] i/o general - purpose input and output port 0.4/i 2 c interface c lock for i2c0/output of pla e lement 2. this pin defaults as an input with the internal pull - up disabled.
data sheet ADUCM310 rev. b page 19 of 27 pin no. mnemonic type 1 description g3 p0.5/sda0/plao[3] i/o general - purpose input and output port 0.5/i 2 c interface d ata for i2c0/output of pla e lement 3. this pin defaults as an input with internal pull - up disabled. g2 p0 .6/scl1/plao[4] i/o general - purpose input and output port 0.6/i 2 c interface c lock for i2c1/output of pla e lement 4. this pin defaults as an input with internal pull - up disabled. g1 p0.7/sda1/plao[5] i/o general - purpose input and output port 0.7/i 2 c interf ace d ata for i2c1/output of pla e lement 5. this pin defaults as an input with internal pull - up disabled. c4 p1.0/sin/eclkin/plai[4] i/o general - purpose input and output port 1.0/uart input p in/external input c lock/input to pla e lement 4 . th e eclkin pin is used for the uart downloader. this pin defaults as an input with internal pull - up disabled. d5 p1.1/sout/placlk1/plai[5] i/o general - purpose input and output port 1.1/uart output p in/pla input cl ock/input to pla e lement 5 . th e placlk1 pin is used for the uart downloader. this pin defaults as an input with internal pull - up disabled. c5 p1.2/pwm0/plai[6] i/o general - purpose input and output port 1.2/pwm0 output/input to pla e lement 6. this pin defaults as an input with internal pull - up disabled. c6 p1.3/pwm1/plai[7] i/o general - purpose input and output port 1.3/pwm1 output/input to pla e lement 7 . this pin defaults as an input with internal pull - up disabled. c7 p1.4/pwm2/sclk1/plao[10] i/o general - purpose input and output port 1.4/pwm2 output/spi1 c lock /ou tput of pla e lement 10. this pin defaults as an input with internal pull - up disabled. c8 p1.5/pwm3/miso1/plao[11] i/o general - purpose input and output port 1.5/pwm3 output/spi1 d ata master in put - slave output/output of pla e lement 11. this pin defaults as an input with internal pull - up disabled. c9 p1.6/pwm4/mosi1/plao[12] i/o general - purpose input and output port 1.6/pwm4 output/spi1 d ata master o utput - slave input/output of pla e lement 12. this pin defaults as an input with internal pull - up disabled. d9 p1.7/irq1/pwm5/ cs1 / plao[13] i/o general - purpose input and output port 1.7/external interrupt request 1/ pwm5 output/spi1 c hip select input/output of pla e lement 13. this pin defaults as an input with internal pull - up disabled. if spi1 is used, configure this pin as cs1 . d4 p2.0/irq2/pwmtrip/placlk2/plai[8] i/o general - purpose input and output port 2.0/external interrupt request 2/ pwm trip input s ource/pla input cl ock/input to pla e lement 8. this pin defaults as an inpu t with the internal pull - up disabled. e8 p2.1/irq3/pwmsync/plai[9] i/o general - purpose input and output port 2.1/external interrupt request 3/ pwm sync i nput/input to pla e lement 9. this pin defaults as an input with the internal pull - up disabled. e4 p2. 2/irq4/ mrst /clkout/plai[10] i/o general - purpose input and output port 2.2/external interrupt request 4/ reset out p in/clock o utput/input to pla e lement 10. this pin defaults as an input with the internal pull - up disabled. c3 p2.3/bm i/o general - purpose input and output port 2.3/bm pin. if this pin is low, then the device enters uart download after the next rest sequence. this pin defaults as an input with the internal pull - up disabled. d7 p2.4/irq5/adcconv/pwm6/plao[18] i/o general - pur pose input and output port 2.4/external interrupt request 5/ external i nput to s tart adc c onversions/pwm6 output/output of pla e lement 18. this pin defaults as an input with the internal pull - up disabled. d8 p2.5/irq6/pwm7/plao[19] i/o general - purpose inp ut and output port 2.5/external interrupt request 6/ pwm7 output/output of pla e lement 19. this pin defaults as an input with the internal pull - up disabled. h1 p2.6/irq7/plao[20] i/o general - purpose input and output port 2.6/external interrupt request 7/ output of pla e lement 20. this pin defaults as an input with the internal pull - up disabled. h2 p2.7/irq8/plao[21] i/o general - purpose input and output port 2.7/external interrupt request 8/ output of pla e lement 21. this pin defaults as an input with the internal pull - up disabled. h3 p3.0/plai[12] i/o general - purpose input and output port 3.0/input to pla e lement 12. this pin defaults as an input with the internal pull - up disabled.
ADUCM310 data sheet rev. b page 20 of 27 pin no. mnemonic type 1 description j3 p3.1/plai[13] i/o general - purpose input and output port 3.1 / input to p la e lement 13. this pin defaults as an input with the internal pull - up disabled. d3 p3.2/plai[14] i/o general - purpose input and output port 3.2/input to pla e lement 14. this pin defaults as an input with the internal pull - up disabled. j1 p3.4/plao[26] i/ o g eneral - purpose input and output port 3.4/output of pla e lement 26. this pin defaults as an input with the internal pull - up disabled. e10 swclk i serial wire debug clock input p in. e9 swdio i/o serial wire debug data input/output input p in. g11 vref_1 .2 ao 1.2 v reference o utput. this pin c annot be used to source current externally. connect this pin to agnd via a 470 nf capacitor. d11 iref ai this pin g enerates the reference current for the idacs. connect this pin to analog ground via a 5 ppm , 3.16 k? external resistor (r ext ). j6 ain0 ai single - ended or differential analog input 0. h7 ain1 ai single - ended or differential analog input 1. j7 ain2 ai single - ended or differential analog input 2. k7 ain3 ai single - ended or differential analog input 3. g8 ain4 ai single - ended or differential analog input 4. this is also the input for the digital comparator. h8 ain5 ai single - ended or differential analog input 5. j8 ain6 ai single - ended or differential analog input 6. k8 ain7 ai single - ended or differ ential analog input 7. l8 ain8 ai single - ended or differential analog input 8. l9 ain9 ai single - ended or differential analog input 9. l4 vdac0 ao 12- bit vdac output 0 , 0 v to 3 v r ange. k4 vdac1 ao 12- bit vdac output 1 , 0 v to 3 v r ange. j9 vdac2 ao 12- bit vdac output 2 , ? 5 v to 0 v r ange. k9 vdac3 ao 12- bit vdac output 3 , ? 5 v to 0 v r ange. j4 vdac4 ao 12- bit vdac output 4 , 0 v to 3 v r ange. h5 vdac5 ao 12- bit vdac output 5 , 0 v to 3 v r ange. h9 vdac6 ao 12- bit vdac output 6 , 0 v to 5 v r ange. h10 vdac7 ao 12- bit vd ac output 7 , 0 v to 5 v r ange. a2 idac0 ao idac0 (100 ma). a3 pvdd_idac0 s power for idac0. b2 cdamp_idac0 ai damping capacitor p in for idac0. connect this pin to the pvdd supply . a10 idac1 ao idac1 (100 ma). a9 pvdd_idac1 s power for idac1. b10 cdam p_idac1 ai damping capacitor pin for idac1. connect this pin to the pvdd supply. b11 idac5 ao idac5 (20 ma). c11 pvdd_idac5 s power for idac5. c10 cdamp_idac5 ai damping capacitor pin for ida c5. connect this pin to the pvdd supply. b1 idac4 ao idac4 ( 20 ma). c1 pvdd_idac4 s power for idac4. c2 cdamp_idac4 ai dampin g capacitor pin for idac4. connect this pin to the pvdd supply. a4 , b4 idac2 ao idac2 (200 ma). a5 , b5 pvdd_idac2 s power for idac2. b3 cdamp_idac2 ai damping c apacitor for idac2. con nect this pin to the pvdd supply. a6 , b6 idac3 ao idac 3 (250 ma). a8 , b8 pvdd_idac3 s power for idac 3. b9 cdamp_idac3 ai damping capacitor pi n for idac 3 . connect this pin to the pvdd supply. a7 , b7 pgnd s power supply ground of the idacs . k5 , g9, l6, j11, h4, l7 agnd1 , agnd2, agnd3, agnd4, agnd5, agnd6 s analog ground p in s.
data sheet ADUCM310 rev. b page 21 of 27 pin no. mnemonic type 1 description j5 dvdd s digital supply p in. this pin is the s upply for the 16 mhz oscillator, pll, por , and digital core , including the flash that requires a regulated 1.8 v supply and a 3 v su pply. f9 vdacv dd s 5 v analog supply pin . l5 , h11 avdd3 , avdd4 s analog supply p in (3.3 v). k3 dvdd_reg1 s output of 2.5 v on c hip low dropout ( ldo ) r egulator. connect a 470 nf capacitor to this pin and dgnd . this regulator supplies the inter - die dig ital interface. l3 dvdd_reg2 s output of 1.8 v on chip ldo regulator. connect a 470 nf capacitor to this pin and dgnd. this regulator supplies flash and the cortex - m3 processor. f10 avdd_reg1 s output of 2.5 v on chip ldo regulator. connect a 470 nf ca pacitor to this pin and dgnd. this regulator supplies the adc. g10 avdd_reg2 s output of 2.5 v on chip ldo regulator. connect a 470 nf capacitor to this pin and dgnd. this regulator supplies the idacs. k6 av neg s ? 5 v supply pin . e1 iovdd1 s 3.3 v gpio supply p in. l2 , d10 dgnd1 , dgnd2 s digital ground p in s. e11 , k1 iovdd2 , iovdd3 s 3.3 v gpio supply p in s. f1, f11 , l1 iognd1, iognd2 , iognd3 s gpio ground p in s. j2 xtalo do output from the crystal oscillator inve rter. if an external crystal is not used , leave this pin unconnected. k2 xtali di input to the crystal oscillator inverte r and i nput to the internal clock generator circuit s. if an external crystal is not used, connect this pin to the dgnd system ground. j10 buf_vref2.5a ao buffered 2.5 v b ias, maximum load = 1.2 ma. connect this pin to agnd via a 100 nf capacitor. k11 buf_vref2.5b ao buffered 2.5 v b ias, maximum load = 1.2 ma. connect this pin to agnd via a 100 nf capacitor. k10 , l10 adc_capn s decoupl ing capacitor conn ection for adc reference buff er. connect this pin to agnd. l11 adc_capp s decoupling capacitor conn ection for adc reference bu ffer. connect this pin to a 4.7 f capacitor and c onnect the other side of the capacitor to the agnd and the a dc_capn pins. a1 , a11, d1, f4, f8, d6, h6 reserved reserved. do not connect to this pin. 1 i is input, i/o is input/output, ao is analog output, ai is analog input, s is supply, do is digital outp ut, and di is digital input.
ADUCM310 data sheet rev. b page 22 of 27 typical performance characteristics 600 0 100 200 300 400 500 0 100 200 300 400 500 600 700 800 900 1000 headroom voltage (mv) load resistance () 13040-008 headroom 25c headroom 125c figure 8 . typical headroom voltage vs. load resistance for vdac7, vdacv dd = 3 v; headroom = vdac v dd ? vdac output voltage 700 600 0 100 200 300 400 500 0 100 200 300 400 500 600 700 800 900 1000 headroom voltage (mv) load resistance () 13040-009 headroom 25c headroom 125c figure 9 . typical headroom voltage vs. load resistance for vdac7, vdacv dd = 5 v; headroom = vdacv dd vdac output voltage 1000 700 900 0 100 200 300 400 800 600 500 0 100 200 300 400 500 600 700 800 900 1000 headroom voltage (mv) load resistance () 13040-010 headroom 125c headroom 25c figure 10 . typical headroom voltage vs. load resi stance for vdac2, av neg = 5 v; headroom = av neg vdac output voltage 450 0 50 100 150 200 250 300 350 400 0 100 200 300 400 500 600 700 800 900 1000 headroom voltage (mv) load resistance () 13040-011 headroom 25c headroom 125c figure 11 . typical headroom voltage vs. load resistance for vdac0, av dd = 3 v; headroom = av dd vdac output voltage 600 500 400 300 200 100 0 0 200 400 600 800 1000 1200 headroom voltage (mv) load resistance () 13040-012 headroom 25c headroom 125c figure 12 . typical headroom voltage vs. load resistance for vdac4, av dd = 3 v; headroom = av dd vdac output voltage 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 0 0.5 1.0 1.5 2.0 2.5 3.0 input current (a) v in (v) ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 13040-013 figure 13 . input current vs. v in , v dd = 3.3 v, t a = 25 c, unbuffered mode, 100 ksps
data sheet ADUCM310 rev. b page 23 of 27 15 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 0 0.5 1.0 1.5 2.0 2.5 3.0 input current (a) v in (v) 13040-014 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 figure 14 . input current vs. v in , v dd = 3.3 v, t a = 25 c, buffered mode, 100 ksps 250 200 150 100 50 0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 headroom (mv) idac output current (ma) 13040-015 +115c +85c +25c ?40c figure 15 . typical idac0 pvdd_idac0 pin voltage headroom vs. output current for different temperatures; pv dd = 1.8 v 250 200 150 100 50 0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 headroom (mv) idac output current (ma) 13040-016 +115c +85c +25c ?40c figure 16 . typical idac1 pvdd_idac1 pin voltage headroom vs. output current for different temperatures; pv dd = 1.8 v 250 200 150 100 50 0 75 100 125 150 175 200 225 headroom (mv) idac output current (ma) 13040-017 +115c +85c +25c ?40c figure 17 . typical idac2 pvdd_idac2 pin voltage headroom vs. output current for different temperatures; pv dd = 1.8 v 600 400 500 300 200 100 0 100 125 150 175 200 225 250 275 headroom (mv) idac output current (ma) 13040-018 +115c +85c +25c ?40c figure 18 . typical idac3 pvdd_idac3 pin voltage headroom vs. output current for different temperatures; pv dd = 1.8 v 160 140 120 100 80 60 40 20 0 5 10 15 25 25 headroom (mv) idac output current (ma) 13040-019 +115c +25c ?40c +85c figure 19 . typical idac4 pvdd_idac4 pin voltage headroom vs. output c urrent for different temperatures; pv dd = 1.8 v
ADUCM310 data sheet rev. b page 24 of 27 160 140 120 100 80 60 40 20 0 5 21 7 9 11 13 15 17 19 headroom (mv) idac output current (ma) 13040-020 +115c +85c +25c ?40c figure 20 . typical idac5 pvdd_idac5 pin voltage headroom vs. output current for different temperatures, pv dd = 1.8 v 90 0 10 20 30 40 50 60 70 80 1.30 1.45 1.50 1.60 1.80 2.00 2.50 snr (db) ext v ref (v) 13040-021 20 80 46.2 61.9 77.2 77.6 78.2 3.0 0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 14 16 output voltage (v) load current (ma) 13040-022 v oh max v oh min v ol max v ol min figure 22 . typical output voltage vs. load current time (not to scale) 3.60 50ms min dvdd (v) dvdd must be above 2.9v for a t least 50ms t o complete por after 50ms dvdd must s t a y above 2.85v including noise excursions 2.90 2.85 13040-024 figure 23 . dvdd power - on requirements
data sheet ADUCM310 rev. b page 25 of 27 recommended circuit and component values figure 24 shows a typical connection diagram for the ADUCM310 . there are four digital supply balls : iovdd1, iovdd2, iovdd3 , and dvdd . decouple t hese balls with a 0.1 f capacitor placed as close as possible to each of the four balls and a 10 f capacitor at the supply source. similarly, the analog supply pins , av dd3 and av dd4 , each require a 0.1 f capacitor placed as close as possible to each ball with a 10 f capacitor at the supply source. the idacs source their output currents from the pv dd supply balls , pvdd_idacx . connect a 100 nf capacitor close to e ach pvdd supply ball. place a t least one 10 f capacitor at the source of the pvdd supply (pvdd_idacx balls ) . the idac output filters depend on a 10 nf capacitor placed between the cdamp_idacx ball and the pvdd _idacx ball . the adc reference requires a 4.7 f capacitor between the adc_ capn and adc_ capp balls. directly connect adc_capn to the analog ground ( agnd ) . the ADUCM310 contains four internal regulators. these regulators require external decoupling capacitors. the dvdd_reg1 and dvdd_reg2 balls each require s a 0.47 f capacitor to the digital ground ( dgnd ) . the avdd_reg1 and avdd_ reg2 balls each require s a decoupling cap acitor to the agnd. to generate an accurate and low drift reference current, connect the iref ball to the analog ground via a low parts per million ( ppm ) 3.16 k ? resistor . connect the vref_1.2 ball to agnd via a 0.4 7 f capacitor. see figure 24 for more details.
ADUCM310 data sheet rev. b page 26 of 27 reset reset adc_capp gnd dgnd swdio tx swclk r ot ce n n oc dr a o b e c a f retni avdd avd d 3 aaav dd4 vref_1 . 2 re f i adc_ ca pn avdd_reg2 avdd_reg1 ag n d 1 ag n d 3 ag n d 2 ag n d4 3.16k ? 0.47f 4.7f 0.47f pgnd ADUCM310 pvdd_idac0 xtali reset dvdd 10k ? pvdd iovdd dvdd dvdd 10 k ? 10f 10k ? 1.6 ? dgnd avdd agnd agnd 0.1f adp7102ard z-3.3-r7 0.1f v in 0.1f dvdd dgnd dgnd1 1 0 f no connect dvdd agnd 0.1 f agnd1 0.1f 0.1f 0.47f 0.47f 0.1f 0.1f dgnd +5v 0.1f agnd vdacv dd av neg ?5v ?0.1f agnd 0.1f 0.1f pgnd xtalo 10nf pvdd_idac1 pvdd_idac2 pvdd_idac2 pvdd_idac3 pvdd_idac3 pvdd_idac4 pvdd_idac5 cdamp_idac0 cdamp_idac1 cdamp_idac2 cdamp_idac3 cdamp_idac4 cdamp_idac5 swdio p1.1/sout/placlk1/plai[5] swclk p1.0/sin/eclkin/plai[4] p2.3/bm dgnd rx f9 d2 j2 k2 a3 a9 a5 a8 c1 c11 b8 b5 b2 b10 b3 b9 c2 c10 l5 h11 g11 d11 f10 g10 k5 g9 l6 j11 a7 b7 e10 e9 d5 c4 c3 k6 100nf 100nf 100nf 100nf 100nf 100nf 100 n f 100 n f 10nf 10nf 10nf 10nf 10nf 10f 10f 0.1f 1.6 ? vin vout sense pg en gnd adp1741acpz 30k ? 10f +2.5v pvdd pgnd pgnd pgnd 10f 10f 10k ? gnd vin vout ss adj en ep 0.1f 0.1f agnd v in v out c p + c p ? sd gnd v sense +5v 10f + ? agnd 0.1f 0.1f 0.1f 31.6k? + + ? ? ?5v iovdd1 iovdd2 iovdd3 dvdd dvdd_ reg1 dvdd_ reg2 dgnd1 dgnd2 iognd1 iognd2 iognd3 e11 e1 k1 l2 d10 f11 f1 l1 k3 l3 adp3605 j5 0.47f adc_ ca pn k10 l10 l11 13040-023 iovdd f igure 24 . typical connection diagram
data sheet ADUCM310 rev. b page 27 of 27 outline dimensions 6.10 6.00 sq 5.90 5.00 ref sq 0.35 0.30 0.25 04-02-2013-a compliant to jedec standards mo-195-ac with the exception to ball count. coplanarity 0.08 0.26 ref a b c d e f g h j k l 7 63 21 5 4 ball diameter 0.50 bsc 0.50 ref detail a a1 ball corner a1 ball corner detail a bottom view top view seating plane 0.93 0.86 0.79 1.200 1.083 1.000 0.223 nom 0.173 min 89 1011 figure 2 5. 112-ball chip scale package ball grid array [csp_bga] (bc-112-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADUCM310bbcz ?10c to +85c 112-ball chip scale package ball grid array [csp_bga] bc-112-4 ADUCM310bbcz-rl ?10c to +85c 112-ball chip scale package ball grid array [csp_bga] bc-112-4 eval-ADUCM310qspz evaluation board with quickstart development system 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2015C2017 analo g devices, inc. all right s reserve d. t rademarks and registered trademarks are the property of their respective owners. d13040-0-7/17(b)

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